Most integrated circuits (ICs) that may require accurate data recovery or data transmission may include a phase-locked loop (PLL) circuit. In general, a PLL is a closed loop feedback system that may generate an output frequency that has a phase and frequency relationship to a reference signal coupled to the PLL input. A typical PLL circuit may require a reference signal coupled to first input of a phase frequency detector circuit, a charge-pump circuit coupled between the phase frequency detector circuit and a controlled oscillator circuit, a loop-filter optionally coupled to the output of the charge-pump circuit, and a divider circuit coupled between the controlled oscillator circuit and the phase frequency detector circuit, where an output of the divider circuit is coupled to a second input of the phase frequency detector circuit.
While the basic PLL architecture has remained nearly the same since it was invented, its implementation in different technologies and for the various applications continue to be a very challenging subject. For example, a PLL serving the task of clock generation in a microprocessor may appear similar to a frequency synthesizer used in a digital signal processor (DSP), but the actual circuit may be designed quite differently.
As technologies continue to advance and ICs require faster clocks to process the fast data rates, PLL designs are pushed to their performance limit. In an example, a PLL employed by a processor a decade ago may have had a frequency range of 200 MHz, in today's processors may require a PLL having a frequency range of 2 GHz. Additionally, the voltage at which the PLL is required to perform has decreased, from typically 5.0 volts to about 1.0 volt.
A problem with PLLs that may have a wide frequency range is lock acquisition. A PLL is considered in lock or in lock acquisition mode is when the divided output frequency and/or phase of the PLL match the frequency and/or phase of the reference signal. Suppose a PLL circuit is initialized, the PLL circuit may generate an initial output frequency outside the design operating range. The divider circuit which provides the divided output may generate a frequency far from the input reference signal, i.e., the PLL is not locked. The transition of the PLL from unlocked condition to a locked PLL condition may be a very nonlinear phenomenon because the phase detector may be receiving unequal frequencies. Even if the PLL may have a wide acquisition range, the loop may not lock unless the difference between the input reference signal and the feedback clock falls within a certain range. Variations in process, voltage, and temperature may amplify the issue of the PLL design and therefore lock acquisition.
Therefore, the need exists for a PLL with initialization circuit which may provide a feedback clock that has a frequency in range of a frequency of the reference signal source. In such instances, it would be advantageous to have a PLL circuit that can have a reliable initial frequency over a range of process, voltage, and temperature variations.